1. Field of the Invention
The present invention relates to a semiconductor memory device and an information processing system, and is particularly suitable for use in a pseudo SRAM (Static Random Access Memory).
2. Description of the Related Art
A pseudo SRAM being one of a semiconductor memory device is a memory in which memory cells for storing data are composed of similar cells with a DRAM (Dynamic Random Access Memory), and an external interface thereof is compatible with an SRAM. The pseudo SRAM has a characteristic of the DRAM which has a large capacity with a low bit cost compared to the SRAM, and an equivalent usability with the SRAM, and the large capacity and an easiness for system designing are realized. For example, a low power (low power consumption) pseudo SRAM is used as a memory (RAM) of, for example, a cellular phone or PDA (Personal Digital Assistants).
FIG. 11 is a block diagram showing a configuration of a conventional pseudo SRAM 111. The pseudo SRAM 111 has a memory cell array 112, an array control circuit 113, a refresh control circuit 114, a chip control circuit 115, an address decoder 116, a data signal control circuit 117, and an interface circuit 118.
The memory cell array 112 is composed of a plurality of memory cells disposed in array state in a row direction and a column direction. As stated above, respective memory cells are 1T-1C type (one transistor one capacitor type) memory cells which are similar to the DRAM. The array control circuit 113 executes a data read operation, a data write operation, and a refresh operation for the memory cells within the memory cell array 112.
The refresh control circuit 114 outputs a request of the refresh operation required for keeping data stored in the memory cells in accordance with a value of a timer included inside thereof.
The chip control circuit 115 decodes a command signal CMD from external (external command) supplied via the interface circuit 118, and outputs the decoded result and a control signal based on the refresh request from the refresh control circuit 114, to the array control circuit 113. As stated later, the command signal CMD is composed of a chip enable signal /CE, an address valid signal /ADV, an output enable signal /OE, and a write enable signal /WE (a sign “/” added to each symbol of signal shows that the signal is a negative logic).
Besides, the chip control circuit 115 performs an arbitration (arbitration process) between an access request (data read and write) by the command signal CMD and the refresh request. In this arbitration, the request generated former is processed in preference.
The address decoder 116 decodes an address signal ADD from external supplied via the interface circuit 118, and outputs the decoded result to the array control circuit 113.
The data signal control circuit 117 controls sending and receiving of data signals between internal and external of a memory in the read operation and the write operation executed in accordance with the command signal CMD.
Incidentally, a clock signal CLK for synchronizing an input/output timing of the command signal CMD and a data signal DQ is inputted to the interface circuit 118 from external, and it is supplied to each functional unit within the pseudo SRAM 111.
Operations in the conventional pseudo SRAM are described with reference to FIG. 12A and FIG. 12B. In FIG. 12A and FIG. 12B, a core operation is a selection operation of the memory cell array 112, in other words, it is an operation that the array control circuit 113 executes for the memory cell array 112. Besides, a Peri operation is an operation of peripheral circuits such as the chip control circuit 115 and the data signal control circuit 117 concerning the memory cell array 112 (array control circuit 113).
FIG. 12A is a timing chart explaining a data read operation in the conventional pseudo SRAM. First, at the time T31, the chip enable signal /CE making a device (pseudo SRAM) in operation state, the address valid signal /ADV showing that the address signal ADD is valid, and the output enable signal /OE are turned to “L”. The chip control circuit 115 decodes the command signal CMD and judges that an access request from external is a data read operation RD (A). Further, the address decoder 116 takes and decodes the address signal ADD.
However, if the refresh request from the refresh control circuit 114 is generated before the time T31 when the access request from external is received, a refresh operation REF is executed at the memory cell array 112 (time T32). Next, the data read operation RD (A) is executed at the memory cell array 112 from the time T33 when the refresh operation REF is terminated, and data 1A, 2A, and 3A of the memory cells corresponding to the decoded results at the address decoder 116 are sequentially read to be outputted as the data signals DQ.
At the time T34, when the chip enable signal /CE is turned to “H”, the chip control circuit 115 indicates the termination of the data read operation RD (A) to the array control circuit 113. Herewith, the data read operation RD (A) executed at the memory cell array 112 is terminated (time T35).
Besides, at the time T35, when the chip enable signal /CE and the address valid signal /ADV is turned to “L”, the chip control circuit 115 decodes the command signal CMD at this time, and judges that the access request from external is a data read operation RD (B). Besides, the address decoder 116 takes and decodes the address signal ADD.
Next, at the time T36 when a refresh entry term TREN is lapsed from the time T35, the data read operation RD (B) is executed at the memory cell array 112, and the data 1B, 2B, 3B, 4B, and 5B are outputted as the data signals DQ. Incidentally, the refresh entry term TREN is provided constantly between the data read/write operations by the access request from external so that the refresh operation at the memory cell array 112 can be executed when the refresh request is generated.
Subsequently, as same as the data read operation RD (A), the chip enable signal /CE is turned to “H” at the time T37, and thereby, the data read operation RD (B) executed at the memory cell array 112 is terminated (time T38).
FIG. 12B is a timing chart explaining a data write operation in the conventional pseudo SRAM. The data write operation shown in FIG. 12B is the same as the data read operation shown in FIG. 12A other than points that the write enable signal /WE is turned to “L” and the output enable signal /OE is kept to “H”, and the data 1A to 3A and 1B to 5B supplied as the data signals DQ are written to the memory cells (times T41 to T48 in FIG. 12B are respectively corresponding to times T31 to T38 in FIG. 12A), and therefore, the explanation thereof will not be given.
In the conventional pseudo SRAM, the data read operation, the data write operation, and so on are executed as shown in FIG. 12A and FIG. 12B.
Further, in recent years, data communications with a large capacity and in real time are performed concerning moving image data and so on, and therefore, a higher-speed operation is required for the pseudo SRAM used as a memory of data communication devices including a cellular phone and so on.
[Patent Document 1] Japanese Patent Application Laid-open No. Hei 11-16346
[Patent Document 2] International Publication No. 98/56004 pamphlet
However, in the conventional pseudo SRAM, as shown in FIG. 12A and FIG. 12B, the refresh entry term TREN is constantly provided, and therefore, as a latency, an access time concerning the access request from external is defined so as to include a case when the refresh request is generated in advance which is the worst case.
As a method to realize a high-speed operation (access) in the pseudo SRAM, the method to shorten the latency to cut down the access time is conceivable. However, if the latency is shortened, a time interval between the data read/write operations by the access requests from external becomes shortened, and there is a possibility that the term corresponding to the refresh entry term TREN cannot be secured. Namely, if the latency is shortened, there is a possibility that the refresh operation cannot be executed between the operations concerning the access requests from external even though the refresh request is generated, and therefore, the data stored in the memory cell may be lost.